Error: **_emif_a10_hps_0: PLL reference clock frequency of 25.0 MHz is invalid. Please select another value, or enable the option to use the recommended value. - Error: **_emif_a10_hps_0: PLL reference clock frequency of 25.0 MHz is invalid. Please select another value, or enable the option to use the recommended value. Description The error message appears because the PLL reference clock setting does not meet the I/O PLL requirements. For further details, refer to the erratum New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP Resolution You will need to apply a higher PLL reference clock frequency setting to meet the I/O PLL performance. Custom Fields values: ['novalue'] Troubleshooting NA False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']