Why are the PCIe Hard IP SDC constraints for tl_cfg* ignored in my SOPC Builder design? - Why are the PCIe Hard IP SDC constraints for tl_cfg* ignored in my SOPC Builder design? Description The PCI Express HardIP constraints for signals tl_cfg* are ignored in the SOPC Builder designs because the altpcierd_tl_cfg_sample module is not used in this mode. As a result, in pcie_compiler_0.sdc, the SDC constraints that are placed after the comment below will be ignored: # The following multicycle path constraints are only valid if the logic use to sample the tl_cfg_ctl and tl_cfg_sts signals Note: These constraints are valid in the Platform Designer and Avalon® streaming HardIP configurations. Resolution N/A Custom Fields values: ['novalue'] Troubleshooting - False ['PCI Express'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']