Why does the HDMI Intel® FPGA IP design example encounter compilation error during simulation when the parameter SUPPORT_AUDIO is set to off? - Why does the HDMI Intel® FPGA IP design example encounter compilation error during simulation when the parameter SUPPORT_AUDIO is set to off? Description Due to a problem starting in version 20.3 of the Intel® Quartus® Prime Pro Edition Software, the HDMI Intel® FPGA IP design example simulation compilation will fail when the parameter SUPPORT_AUDIO is set to off. This is due to the HDMI Intel® FPGA IP design example simulation testbench trying to access the HDMI audio port that has been disabled in the HDMI Intel® FPGA IP. Resolution This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1509008639 True ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.2 20.3 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']