Customizing Altera® Stratix® 10, Altera Arria® 10 & Altera Cyclone® 10 GX FPGA Hard IP for PCI Express* - 27 Minutes In this course, you will learn how to customize the Hard IP PCI Express* when building a PCI Express Endpoint or Root Port design targeting the Altera® Stratix® 10, Altera® Arria® 10 or Altera® Cyclone 10 GX FPGA devices. You will see how to select options in the Hard IP parameter editor to customize the Hard IP per your specific design requirements. To use the parameter editor, you will learn about two flows in which to incorporate the Hard IP into an FPGA design, using the IP Catalog found in the Platform Designer system building tool or the IP Catalog found in the Altera® Quartus® Prime Pro development suite. Course Objectives At course completion, you will be able to: Create a PCI Express design in an Altera® Stratix® 10, Altera® Arria® 10 or Altera® Cyclone 10 GX FPGA using 1) Platform Designer system design tool 2) Altera® Quartus Prime Pro IP Catalog Customize your Altera® FPGA Hard IP for PCI Express instance using IP parameter editor Skills Required Some understanding of the PCI Express Protocol specification is helpful, but not required Familiarity with common high-speed transceiver architecture or viewing the transceiver basics course Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime Pro software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPCICUSTOMG10. FPGA_OPCICUSTOMG10. <p>Customizing Altera Stratix 10, Altera Arria 10 & Altera Cyclone 10 GX FPGA Hard IP for PCI Express*</p>