When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are malformed packets detected after assertion of the o_sl_tx_lanes_stable signal? - When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are malformed packets detected after assertion of the o_sl_tx_lanes_stable signal? Description Due to a problem with Intel® Quartus® Prime software version 18.0 and earlier, malformed packets with CRC errors can be detected in the MAC statistic counters when transmitting packets using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode after assertion of the o_sl_tx_lanes_stable signal. Resolution To work around this problem in Intel® Quartus® Prime software version 18.0 and earlier, wait for 46610 clock cycles in simulation or 163840 clock cycles in hardware after the assertion of the o_sl_tx_lanes_stable signal following link reset or power up before transmitting jumbo data packets to the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode. This problem has been fixed starting in Intel® Quartus® Prime Pro software version 18.0.1. Custom Fields values: ['novalue'] Troubleshooting 587836 True ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0.1 18.0 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']