In simulation of the Stratix® V Reconfiguration Controller, why do my ATX Calibration Registers all read "DEADBEEF"? - In simulation of the Stratix® V Reconfiguration Controller, why do my ATX Calibration Registers all read "DEADBEEF"? Description Simulation of the transceiver ATX PLL calibration registers in Stratix® V GX devices is not supported. However, the calibration processes are fully functional in silicon. Resolution You should not attempt to access these registers in simulation. Custom Fields values: ['novalue'] Troubleshooting 2205752845 False ['L-Tile H-Tile Transceiver ATX PLL Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']