Why is the "Additional CK/CK# phase" option grayed out in the parameter editor for Stratix® V and Arria® V GZ devices? - Why is the "Additional CK/CK# phase" option grayed out in the parameter editor for Stratix® V and Arria® V GZ devices? Description The "Additional CK/CK# phase" option is grayed out in the parameter editor because custom phase shifts for the memory clock is not supported for that device and protocol. Resolution The Stratix® V and Arria® V GZ devices only support this option for UniPHY-based DDR2 memory controllers with a frequency of 150 MHz or above. Custom Fields values: ['novalue'] Troubleshooting 1408189285 False ['DDR3 SDRAM Controller with UniPHY IP'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GZ FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']