Aldec simulation fails for the 40GbE and 100GbE MAC and PHY IP Core - Aldec simulation fails for the 40GbE and 100GbE MAC and PHY IP Core Description Generated file sets for the 40GbE and 100GbE MAC and PHY IP cores with the 12.1 release of the Quartus II software include an Aldec simulation file set. However, Altera does not officially support Aldec simulation for the 12.1 release of the IP cores. Resolution Report any simulation issues directly to Aldec ( www.aldec.com ). Custom Fields values: ['novalue'] Troubleshooting novalue True ['Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']