Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ and Stratix® V GX/GT devices? - Why doesn't the tx_cal_busy signal assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ and Stratix® V GX/GT devices? Description The tx_cal_busy signal will not assert if ATX PLL calibration is started through the Avalon Memory Mapped interface on Arria® V GZ and Stratix® V GX/GT devices. The tx_cal_busy signal is only asserted at initial runtime calibration or if you reset the reconfiguration controller. To determine whether the ATX PLL calibration process is complete, you can read the ATX PLL control and status register. The busy status is bit 8 of the control and status register at address offset 7'h32. Resolution This problem is fixed starting with the V-Series Transceiver PHY IP Core User Guide version 14.1. Related Articles How can I meet the Stratix V and Arria V GZ device ATX PLL calibration requirement that the transceiver reference clock must be present at the start of device configuration if I use the FPGA to program my clock synthesizer device? How can I recalibrate the Stratix V and Arria V GZ device ATX PLLs? Custom Fields values: ['novalue'] Troubleshooting 2205756435 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software'] 14.1 13.1 ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']