Why do I get the same timing results for all timing corners when using Design Space Explorer? - Why do I get the same timing results for all timing corners when using Design Space Explorer? Description In the Quartus® II software, Design Space Explorer (DSE) may report the same results for fall timing corners if your Synopsys Design Constraints ( .sdc ) file contains a set_operating_conditions command. Resolution To avoid this behavior, remove the set_operating_conditions command from the .sdc file. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']