Cyclone IV E implementing SPI - Cyclone IV E implementing SPI I'm using EP4CE10 as a SPI Master to control LMX2820, then find the control words are not written correctly. Does the I/O pin selection and configuration has special requirement? Replies: Re: Cyclone IV E implementing SPI Also, the RFoutAP wire must be connected, so that the ADC connected to FPGA wont interfere with SPI transmission. The dangling connection seems to either interfere with LMX2820 or interfere with my AD9226 ADC. I also find, connecting grounds of FPGA and LMX2820 may offer benefit. Replies: Re: Cyclone IV E implementing SPI Hi, Thanks for your update on the issue and the workaround you discovered for your issue. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Replies: Re: Cyclone IV E implementing SPI I find that adding extra guard time between transmission of data enables successful register write. For 100m clock rate, 40 cycles are enough. Also, pin voltage must be set to 3.3V LVTTL. The repository I mentioned can successfully write individual 24-bits data and by adding guard time can write data bytes continuously. Replies: Re: Cyclone IV E implementing SPI Hi, We apologies for the lack of documentation from our side. I hope the pervious links may help you in your design work. Replies: Re: Cyclone IV E implementing SPI Hi, Regarding the Pin Out, for your device is: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/ep4ce10.pdf https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv We do not have any example on SPI for Cyclone IV. Maybe you could check these out, see if it helps: https://forum.digikey.com/t/spi-3-wire-master-vhdl/12743 http://s100computers.com/My%20System%20Pages/FPGA%20Board%20V2/V2_FPGA_CIRCUITS/SPI_Master/SPI_Master.htm Replies: Re: Cyclone IV E implementing SPI signal Tap II from Quatus indicates the timing is right. I'm switching to STM32H7 for another try. The STM32F1 worked, but SPI baud-rate is too low and ADC sampling rate is not enough. Replies: Re: Cyclone IV E implementing SPI I've tried several spi_master code base, but none was able to program lmx2820 registers correctly. None of them give desired result. After reading register content back with official software TICS Pro, some registers show separate content other than written in. One example code repl https://github.com/halftop/Interface-Protocol-in-Verilog.git . Replies: Re: Cyclone IV E implementing SPI Hi, Could you share the Quartus design? Have you tried to do a signal tap to see if the output are as expected?