Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? - Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi, I am building on top of the Agilex 5E GSRD design. My goal is not to use the HPS-side DDR for the FPGA accelerator data buffer. Instead, I want the data path to be: ARM/HPS writes input data -> HPS2FPGA bridge -> FPGA-side DDR4 via EMIF_IO96B_DDR4COMP FPGA IP reads input data from FPGA-side DDR4 FPGA. IP computes and writes result back to FPGA-side DDR4 ARM/HPS reads result back from FPGA-side DDR4 via HPS2FPGA My current Platform Designer connection is roughly: HPS hps2fpga master -> EMIF_IO96B_DDR4COMP AXI memory-mapped slave FPGA accelerator memory port -> same EMIF_IO96B_DDR4COMP EMIF pins -> external DDR4 The EMIF configuration and DDR4 pin assignments are matched carefully against the example design: /agilex5e_installer_package/examples/bts_emif/ bts_ddr4_2b downloaded from the agilex5e installer package. I also tested the original bts_ddr4_2b style flow in the example using: JTAG -> pattern adaptor -> EMIF -> DDR4 and DDR4 read/write tests pass without errors. So the FPGA-side EMIF DDR4 calibration/pattern test appears to work. However, when I try to access the same FPGA-side DDR4 from Linux on HPS through the HPS2FPGA bridge using devmem2, the access fails badly. For example, accessing the HPS2FPGA mapped address causes a bus error / fatal SError. One example log: root@agilex5dka5e065bb32aes1:~# devmem2 0x40000000 w /dev/mem opened. [ 1017.877669] SError Interrupt on CPU2, code 0x00000000be000011 -- SError [ 1017.877707] CPU: 2 PID: 791 Comm: devmem2 Not tainted 6.12.19-altera-g7b497655d942 #1 [ 1017.877717] Hardware name: SoCFPGA Agilex5 SoCDK (DT) ... [ 1017.877814] Kernel panic - not syncing: Asynchronous SError Interrupt ... Bus error For comparison, I connected the same HPS2FPGA bridge to an on-chip memory in the FPGA fabric. Accessing that on-chip memory from HPS with devmem2 works correctly . So the HPS2FPGA bridge itself seems functional. Current observations: HPS2FPGA -> on-chip memory works. JTAG -> pattern adaptor -> EMIF -> DDR4 works. EMIF calibration appears to pass. HPS2FPGA -> EMIF DDR4 causes SError / bus error / Linux kernel panic. Here is my current Platform Designer connection. In the screenshot, you can see that I copied over the EMIF-driving logic from the installer package. For emif_axi4, one connection goes to my IP’s memory port, and the other goes to the HPS hps2fpga interface, although that HPS connection is not shown in this screenshot. Does anyone have any clues about what might be wrong here? Is this expected to work, or is this use case currently not supported, i.e. HPS reading/writing data directly to FPGA-side DDR through HPS2FPGA while an FPGA IP also accesses the same DDR through the EMIF AXI4 interface? If any additional files would be helpful, I can provide them. Thank you in advance! Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Thank you very much for your help! Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi amsssss123 From the screenshot, the connections looks okay. For the lwhps2fpga_clk, it could be connected to the clk_100 when the hps2fpga_clk is connected to a different clock. Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi, Thank you for the clarification! I updated the design according to your suggestion: emif_io96b_ddr4comp_0.s0_axi4_clock_out -> subsys_hps.hps2fpga_clk subsys_hps.h2f_reset -> subsys_hps.hps2fpga_rst Could you please check whether my current connections are correct, and whether there are any other incorrect parts? I have one follow-up question about the other HPS bridge clocks. For example, lwhps2fpga_clk is still connected to clk_100 in my design. This clock is used for lightweight HPS-to-FPGA accesses, such as CSR/control registers, not for the main EMIF s0_axi4 data path. Is it okay for lwhps2fpga_clk and other unrelated HPS-side control clocks to remain on clk_100, even though hps2fpga_clk is now driven by emif_io96b_ddr4comp_0.s0_axi4_clock_out and therefore has a different frequency? Thank you again for your help! Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi amsssss123 Yes the hps2fpga_clk and the hps2fpga_rst are referencing to the hps2fpga_axi_clock and hps2fpga_axi_reset mentioned. For the EMIF Clock in the first screenshot it is shows the Access Mode of the EMIF is in Sync Mode with a clock out present, it should be connected to the hps2fpg_clk. If it is in Async Access Mode both hps2fpg_clk and s0_axi4_clk should be connected to the same clock source. Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi, Thank you very much for your reply! I have attached the screenshot of the HPS block. I checked my current design, and you are right, the two signals you mentioned were not connected. I also went through the documentation again, and it does say that the h2f_reset signal needs to be connected to the hps2fpga_axi_reset signal for proper bridge operation. I missed that before. I do have a few follow-up questions: In my screenshot, the HPS block ports are named hps2fpga_clk and hps2fpga_rst. Are these the same as the hps2fpga_axi_clock and hps2fpga_axi_reset signals mentioned in the documentation and in your reply? For the clock connection, if I connect the EMIF s0_axi4_clock_out to the hps2fpga_axi_clock, do I also need to move the related HPS-side AXI/control logic to the same s0_axi4_clock_out domain? Currently, the HPS-side logic is connected to clk_100, which is 100 MHz. My understanding from the EMIF documentation is that s0_axi4_clock_out is one-quarter of the memory clock frequency, i.e. mem_CK / 4. Please correct me if I misunderstood this. Since the DDR frequency is currently 800 MHz, I assume the EMIF clock output should be around 200 MHz. In that case, if only the HPS-to-FPGA AXI clock is changed to the EMIF clock output, the related HPS-side logic would no longer all be in the same clock domain. Would that be okay, or should all related HPS-side AXI/control logic also be moved to the EMIF clock domain. Thank you for your help and support! Replies: Re: Agilex 5E: How to access FPGA-side EMIF DDR4 from HPS through HPS2FPGA? Hi amsssss123 Could you also share a screenshot of the HPS block? There are a thins that would need to check: Is the h2f_reset signal connected to the hps2fpga_axi_reset signal? Is the s0_axi4_clock_out connected to the hps2_fpga_axi_clock? Could you add in a logic to check the s0_axi4_ctrl_ready before any R/W to the EMIF happen.