What may cause the Intel® Stratix® 10 DDR4 IP to violate the Exit Power Down to Refresh Minimum Delay (tXP)? - What may cause the Intel® Stratix® 10 DDR4 IP to violate the Exit Power Down to Refresh Minimum Delay (tXP)? Description Due to a problem in the Intel® Stratix® 10 DDR4 IP, the Exit Power Down to Refresh Minimum Delay (tXP) may be violated because the controller may not properly gate the Logical Rank Refresh request with the tXP timer which causes the request to execute immediately after exiting the Power Down. Therefore, the Logical Rank Refresh request may be ignored which may eventually lead to insufficient refreshes. This problem may occur when the Enable Auto Power-Down option is turned ON, the memory format is selected as either RDIMM or LRDIMM , the Chip ID width is set to any 3DS configuration, and the Number of physical ranks per DIMM is set to a value greater than 1. Resolution To work around this problem, select the Enable User Refresh Control option and execute additional refresh requests. Custom Fields values: ['novalue'] Troubleshooting 1408170524 False ['External Memory Interfaces Stratix® 10 FPGA IP', 'Memory Interfaces and Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 20.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']