Why do writes to an M20K fail after a Partial Reconfiguration? - Why do writes to an M20K fail after a Partial Reconfiguration? Description Due to a problem in the Quartus® Prime Pro Edition Software version 23.2 and later, you might see a functional failure when writing to an M20K RAM after Partial Reconfiguration. This problem only occurs in design targets an Agilex™ 7 F/I-Series devices and either of these conditions The Compiler Optimization Mode is not set to Performance The design has 2 or more abutting PR partitions that share the same clock. Resolution To workaround this problem, perform these options Recompile the design with Compiler Optimization Mode set to one of the Performance options. Ensure there is a separation (at least one row/column space) between abutting PR partition routing regions for the designs with more than one PR region. Note: This restriction does not apply to Agilex™ 7 M-series production devices. Related Articles Why does my M20K RAM write fail after a Partial Reconfiguration operation? Custom Fields values: ['novalue'] Troubleshooting 14020545714 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.1 23.2 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']