Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2? - Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2? Description Due to a problem with the CIC Intel® FPGA IP in Intel® Quartus® Prime version 18.1 software, you may observe the above problem if the value of "Number of stages" is of power of 2 and the "Filter type" is Interpolator. Resolution There is no workaround for this problem. This problem will be fixed in a future version of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting 1507322692, 1409080675 False ['CIC IP'] ['FPGA Dev Tools Quartus® Prime Software Pro', 'FPGA Dev Tools Quartus® Prime Software Standard'] novalue 18.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'MAX® 10 10 FPGAs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']