Why does the Intel Agilex® FPGA HPS inadvertently enters a Cold Reset (HPS_COLD_nRESET pin)? - Why does the Intel Agilex® FPGA HPS inadvertently enters a Cold Reset (HPS_COLD_nRESET pin)? Description According to the Intel Agilex ® 7 Device Data Sheet , the minimum reset pulse width for the HPS_COLD_nRESET signal is 3 msec (Trst0). If a pulse width of less than 3 msec occurs on this pin, an unintentional reset may occur. The HPS system may inadvertently detect pulses as short as approximately 0.3 msec in width. Resolution To work around this problem, implement an external hardware debounce circuitry that will hold the HPS_COLD_nRESET signal asserted for a minimum of 3 msec. Custom Fields values: ['novalue'] Troubleshooting 1509098741 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 21.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']