How can I generate IBIS models for Arria 10 or MAX 10 JTAG pins? - How can I generate IBIS models for Arria 10 or MAX 10 JTAG pins? Description You can generate IBIS models for Arria® 10 device or MAX® 10 device JTAG pins in the Quartus® Prime software version 15.0 and later. Resolution To generate IBIS models for Arria 10 device or MAX 10 device JTAG pins directly from the Quartus Prime software, do the following : 1. Ensure your EDA Tool Settings are correctly enabled to generate IBIS files Settings > EDA Tool Settings > Board-Level > Board-level Signal Integrity Analysis Format: IBIS 2. Include a JTAG IP in your design (e.g. Altera Soft Core JTAG I/O IP). 3. Run compilation and you will see the IBIS file in the directory below: <design_top_directory>/board/ibis/<design_top.ibs>. This file will contain models for the JTAG pins. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']