Why does Quartus II assigns incorrect I/O standard for the refclk pin on Arria II GX/GZ and Stratix IV GX/GT devices for ALTGX instances? - Why does Quartus II assigns incorrect I/O standard for the refclk pin on Arria II GX/GZ and Stratix IV GX/GT devices for ALTGX instances? Description Quartus ® II incorrectly assigns I/O standard for the refclk pin on Arria ® II GX/GZ and Stratix ® IV GX/GT devices for ALTGX instances, if you do not manually assign the correct refclk I/O standard for the pll_inclk port. Quartus II auto-assigns the general default I/O standard set by user in the design. This leads to an incorrect setting of the I/O standard of 2.5V to the REFCLK pin. Resolution Manually assign the correct refclk IO standard for the pll_inclk pin. This issue will be fixed in future Quartus II release. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1.1 ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Stratix® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']