Why are the rx_pcs_ready signal and bit[0] of the PHY_RXPCS_STATUS register (offset 0x326) not asserted for the Intel Low Latency 40- and 100-Gbps Ethernet IP cores? - Why are the rx_pcs_ready signal and bit[0] of the PHY_RXPCS_STATUS register (offset 0x326) not asserted for the Intel Low Latency 40- and 100-Gbps Ethernet IP cores? Description Due to a problem with the Intel® Low Latency 40- and 100-Gbps Ethernet IP cores, rx_pcs_ready and bit[0] of the PHY_RXPCS_STATUS register will not assert during link training, if bit[0] of the PHY_SCLR_FRAME_ERROR register (offset 0x324) is set. Resolution Bit[0] of the PHY_SCLR_FRAME_ERROR register should be set only when reading the PHY_FRAME_ERROR register (offset 0x323). It should be de-asserted soon after reading the PHY_FRAME_ERROR register (offset 0x323). This is not scheduled to be fixed in any future Quartus® Prime software release. Custom Fields values: ['novalue'] Troubleshooting FB: 364821; False ['Low Latency 40G 100G Ethernet'] ['novalue'] novalue novalue ['Arria® 10 FPGAs and SoCs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']