Errors in the Configuration Pins Summary for Intel® Cyclone® 10 LP Devices - Errors in the Configuration Pins Summary for Intel® Cyclone® 10 LP Devices Description Issue 523215 : Chapter 6 Configuration and Remote System Upgrades, section 6.3.3 Device Configuration Pins, version 2017.12.22 Table 47. Configuration Pins Summary for Intel® Cyclone® 10 LP Devices has the following errors. The configuration pin name of nCSO/FLASH_nCE is incorrect. It should be nCSO. The Input/Output column of CLKUSR incorrectly says Output. It should be Input. The Input/Output column of nCEO incorrectly says Input. It should be Output. DEV_OE pin is missing. The location is Bank 5. It is an input pin, is not a dedicated pin and is powered by VCCIO. The configuration mode is Optional. Resolution Bank Configuration Pins Dedicated Input/Output Powered By Configuration Mode 1 (incorrect) nCSO/FLASH_nCE => (correct) nCSO - Output VCCIO AS 6 CLKUSR - (incorrect) Output => (correct) Input VCCIO Optional 6 nCEO - (incorrect) Input => (correct) Output VCCIO Optional, all modes 5 DEV_OE - Input VCCIO Optional Custom Fields values: ['novalue'] Troubleshooting FB: 523210; False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']