Which clock is the reference clock for the HPS Ethernet MDC clock? - Which clock is the reference clock for the HPS Ethernet MDC clock? Description The correct reference clock for the HPS Ethernet clock is l4_mp_clk. The V HPS Address Map, emac->gmacgrp->GMII_Address->cr incorrectly states the CSR clock range selection determines the frequency of the MDC clock according to l3_sp_clk frequency. Resolution This problem is resolved starting with release 15.1 of the HPS Address Map. Custom Fields values: ['novalue'] Troubleshooting n/a False ['Ethernet'] ['FPGA Dev Tools Quartus II Software'] 15.1 13.0 ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']