Why is no TX and RX data when using multilane bonded configurations of the Agilex™ 5 GTS PMA/FEC Direct PHY FPGA IP running at 17.16 Gbps? - Why is no TX and RX data when using multilane bonded configurations of the Agilex™ 5 GTS PMA/FEC Direct PHY FPGA IP running at 17.16 Gbps? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the tx_ready signal of one of the lanes in the multilane configuration of the Agilex™ 5 GTS PMA/FEC Direct PHY FPGA IP is not being asserted at the max rate of 17.16Gbps. This causes no TX and RX data at a max rate of 17.16 Gbps under bonding configuration. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. Custom Fields values: ['novalue'] Errata 15016686620 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']