How do I resolve timing closure warnings when compiling a design with the JESD204C Intel® FPGA IP in base only mode? - How do I resolve timing closure warnings when compiling a design with the JESD204C Intel® FPGA IP in base only mode? Description You may see some or all of the warning messages below when compiling a design with the JESD204C Intel® FPGA IP in base only mode in the Intel® Quartus® Prime Pro Edition software versions 20.1 or 20.2. Message ID Message text 17897 No destination clock period was found satisfying the set_net_delay assignment from "[get_keepers {mac_tx|j204c_tx_base_inst|j204c_tx_gearbox_inst|tx_gb[0].j204c_tx_gb_perlane_inst|tx_gb_fifo_inst|j204c_tx_dcfifo132b_m20k|dcfifo_component|auto_generated|delayed_wrptr_g*}]" to "[get_keepers {mac_tx|j204c_tx_base_inst|j204c_tx_gearbox_inst|tx_gb[0].j204c_tx_gb_perlane_inst|tx_gb_fifo_inst|j204c_tx_dcfifo132b_m20k|dcfifo_component|auto_generated|rs_dgwp|dffpipe*|dffe*}]". This assignment will be ignored. 332182 No path is found satisfying assignment "set_max_skew -from [get_keepers {mac_tx|j204c_tx_base_inst|j204c_tx_gearbox_inst|tx_gb[0].j204c_tx_gb_perlane_inst|tx_gb_fifo_inst|j204c_tx_dcfifo132b_m20k|dcfifo_component|auto_generated|*rdptr_g*}] -to [get_keepers {mac_tx|j204c_tx_base_inst|j204c_tx_gearbox_inst|tx_gb[0].j204c_tx_gb_perlane_inst|tx_gb_fifo_inst|j204c_tx_dcfifo132b_m20k|dcfifo_component|auto_generated|ws_dgrp|dffpipe*|dffe*}] -get_skew_value_from_clock_period src_clock_period -skew_value_multiplier 0.800 ". This assignment will be ignored. 332174 Ignored filter at intel_jesd204c.sdc(81): -group could not be matched with a clock 332049 Ignored create_clock at intel_jesd204c.sdc(64): Argument is an empty collection 332054 Assignment set_clock_groups is accepted but has some problems at intel_jesd204c.sdc(81): Argument -group with value -group {j204c_txphy_clk[0]} -group {j204c_txphy_clk[1]} -group {j204c_txphy_clk[2]} -group {j204c_txphy_clk[3]} -group {j204c_txphy_clk[4]} -group {j204c_txphy_clk[5]} -group {j204c_txphy_clk[6]} -group {j204c_txphy_clk[7]} could not match any element of the following types: ( clk ) 332060 Node: j204c_txphy_clk was determined to be a clock but was found without an associated clock assignment. Resolution To workaround this issue in the Intel® Quartus® Prime Pro Edition software versions 20.1 or 20.2 replace certain lines in the intel_jesd204c.sdc file as shown below. simplex rx base only( ... /intel_jesd204c_rx_191/synth/intel_jesd204c.sdc ): change from: 77 set overall_clock "" 78 for { set j 0} { $j < 4} { incr j} { 79 append overall_clock "-group {j204c_rxphy_clk[$j]} " 80 } 81 set_clock_groups -asynchronous -group {j204c_rx_avs_clk} -group {j204c_rxlink_clk j204c_rxframe_clk} $overall_clock to 77 set overall_clock "" 78 set clock_grp "" 79 for { set j 0} { $j < 4} { incr j} { 80 append overall_clock "-group {j204c_rxphy_clk[$j]} " 81 } 82 set clock_grp_tmp {set_clock_groups -asynchronous -group {j204c_rx_avs_clk} -group {j204c_rxlink_clk j204c_rxframe_clk} } 83 append clock_grp $clock_grp_tmp $overall_clock 84 eval $clock_grp simplex tx base only( .../intel_jesd204c_tx_191/synth/intel_jesd204c.sdc ): change from: 63 for {set i 0} { $i < 4} {incr i} { 64 eval {create_clock -name "j204c_txphy_clk[$i]" -period 3.945ns [get_ports j204c_txphy_clk[$i]]} 65 } . . . 78 for { set j 0 } { $j < 4} { incr j} { 79 append overall_clock "-group {j204c_txphy_clk[$j]} " 80 } 81 eval {set_clock_groups -asynchronous -group {j204c_tx_avs_clk} -group {j204c_txlink_clk j204c_txframe_clk} $overall_clock} to 64 eval {create_clock -name "j204c_txphy_clk" -period 3.945ns [get_ports j204c_txphy_clk]} . . . 79 set clock_grp "" 80 append overall_clock {-group {j204c_txphy_clk} } 81 set clock_grp_tmp {set_clock_groups -asynchronous -group {j204c_tx_avs_clk} -group {j204c_txlink_clk j204c_txframe_clk} } 82 append clock_grp $clock_grp_tmp $overall_clock 83 eval $clock_grp duplex base only( .../intel_jesd204c_tx_191/synth/intel_jesd204c.sdc ): change from: 64 create_clock -name "j204c_rxphy_clk[$i]" -period 3.945ns [get_ports j204c_rxphy_clk[$i]] 65 create_clock -name "j204c_txphy_clk[$i]" -period 3.945ns [get_ports j204c_txphy_clk[$i]] 66 } . . . 86 set overall_clock "" 87 for { set j 0 } { $j < 4} { incr j} { 88 append overall_clock "-group {j204c_rxphy_clk[$j]} -group {j204c_txphy_clk[$j]} " 89 } 90 set_clock_groups -asynchronous -group {j204c_tx_avs_clk j204c_rx_avs_clk} -group {j204c_txlink_clk j204c_txframe_clk j204c_rxlink_clk j204c_rxframe_clk } $overall_clock to 64 create_clock -name "j204c_rxphy_clk[$i]" -period 3.945ns [get_ports j204c_rxphy_clk[$i]] 65 } 66 eval create_clock -name "j204c_txphy_clk" -period 3.945ns [get_ports j204c_txphy_clk] . . . 87 set overall_clock "" 88 set clock_grp "" 89 append overall_clock {-group {j204c_txphy_clk} } 90 set clock_grp_tmp {set_clock_groups -asynchronous -group {j204c_tx_avs_clk} -group {j204c_txlink_clk j204c_txframe_clk} } 91 for { set j 0} { $j < 4} { incr j} { 92 append overall_clock "-group {j204c_rxphy_clk[$j]} " 93 } 94 set clock_grp_tmp {set_clock_groups -asynchronous -group {j204c_rx_avs_clk} -group {j204c_rxlink_clk j204c_rxframe_clk} } 95 append clock_grp $clock_grp_tmp $overall_clock 96 eval $clock_grp note: all the clock period values are dependent on user selected values. This problem is fixed starting with Intel Quartus Prime Pro Edition software version 20.3. Custom Fields values: ['novalue'] Troubleshooting 1508146113 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 20.3 20.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']