Why do I get fitter errors when compiling a DDR3 UniPHY-based controller design in the Platform Designer? - Why do I get fitter errors when compiling a DDR3 UniPHY-based controller design in the Platform Designer? Description You might see the following errors when trying to compile the HPS design generated in the Platform Designer: Error: Input port DATAIN on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port DATAIN is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error: Input port ENA on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port ENA is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Error: Input port UPDATE on atom "<Hierarchy>.config_1", which is a cyclonev_io_config primitive, is not legally connected and/or configured Info (129003): Input port UPDATE is driven by a constant signal, but the Compiler expects this input port to be connected to a real signal Resolution This happens when you use the Platform Designer directly through deferred generation. For example, your .qsf file includes the .qsys file and the intellectual property (IP) is generated on the fly. This does not work in a current version of the Quartus II software. The correct design flow is to replace the .qsys file in your project file list with the .qip file then recompile your design. Custom Fields values: ['novalue'] Troubleshooting 1408013872 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] No plan to fix No plan to fix ['Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']