In the table of Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices, what do 170-230 MHz internal clock and 250 MHz internal clock represent? - In the table of Maximum Configuration Time Estimation for Intel® Stratix® 10 Devices, what do 170-230 MHz internal clock and 250 MHz internal clock represent? Description What do the 170-230 MHz internal clock and 250 MHz internal clocks that are stated in the Maximum Configuration Time Estimation for Intel®Stratix® 10 Devices table represent? Resolution The parameters 170-230 MHz and 250 MHz represent the clock for SDM operations. The frequency depends on the setting of the configuration clock source in the Intel® Quartus® Prime Software. Custom Fields values: ['novalue'] Troubleshooting 1507120698 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']