Why does the HPRXM interface of the Intel® Arria® 10 or Intel® Cyclone® 10 Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* output incorrect byte enables for burst write transactions? - Why does the HPRXM interface of the Intel® Arria® 10 or Intel® Cyclone® 10 Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* output incorrect byte enables for burst write transactions? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.1 and earlier, the Intel® Arria® 10 or Intel® Cyclone® 10 Avalon® Memory-Mapped (Avalon-MM) DMA Interface for PCI Express* configured with a 128-bit interface and burst-capable RXM BAR2 port may output incorrect byte enables on the first and last write transactions on the HPRXM interface for a burst write. Resolution This problem is fixed beginning with the Intel® Quartus® Prime Pro Edition Software version 22.2. Custom Fields values: ['novalue'] Troubleshooting 14016379169 False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 18.1.1 ['Arria® 10 GX FPGA', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']