Is differential high-speed transceiver logic (HSTL) supported on center and corner phase locked loops (PLL) in my StratixTM device? - Is differential high-speed transceiver logic (HSTL) supported on center and corner phase locked loops (PLL) in my StratixTM device? Description Yes, differential HSTL is supported on the center and corner PLLs in Stratix devices. Quartus® II versions 3.0 SP2 and lower do not have support for this IO standard on the center and corner PLL clock input pins. The next version of Quartus II will support this feature. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Stratix® FPGAs'] ['novalue'] ['novalue'] ['novalue']