Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy - Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Hi, 1. The Agliex 7 F Series EMIF User Guide page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F series evaluation board DDR4 memory vendor datasheet (thisis publicly available one for the MT40A2G8VA used on above linked eval board) states RESET must be low while power rails ramp up as pictured below which implies it should be instead pulled down to ground. Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies? From above public Micron datasheet 2. Figure 143 in section 6.5.6.1 of Agilex 7 EMIF User Guide shows ADDR/CMD clock terminated to VDD through R and C network. Altera F Tile eval board has ADDR/CMD clock terminated to GND through R and C network. Can Altera explain why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation? From Eval board Thanks! Replies: Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Thanks Azim for the clarification. I marked your answer as solution. Replies: Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Hi Steve9 , We will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions. Thank you for engaging with us! Regards, Adzim Replies: Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Hi Steve9 , ASIC or ASSP can drive low at power up sequence, but FPGA needs configuration to download the programming file and during configuration time, pin is flowed and pull up on the board. This is nature of the FPGA pins. But after configuration is done FPGA will assert low during initialization. So it goes like High -> Low -> High So the FPGA still can drive the pin low or high regardless the termination scheme. Regards, Adzim Replies: Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Thanks Adzim. For point 1, the reset_n pin is only connected from Agilex output to SDRAM chip inputs with pullup, so the only thing that can drive the reset_n pin is the Agilex right? And the Agilex can't drive signals until it's powered up. So I'm not sure what you mean by "the power need to apply to reset_n pin". It seems like it would not be possible to meet the datasheet power-up sequence that "Reset_n should be maintained below 0.2 x VDD while supplies ramp up" with the suggested pullup. For point 2, understood. Replies: Re: Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy Hi Steve9 , " Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies? " The power need to apply to reset_n pin at power-up sequence as mention in datasheet. " why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation? " There are multiple termination scheme that has been used to terminate the clk signal. You can also terminate the signal to VDD. Also can terminate to both VDD and GND. I think the board designer should identify which termination scheme that suitable for their board. Regards, Adzim