Why do I need to perform the IOPLL Intel® FPGA IP Upgrade in the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? - Why do I need to perform the IOPLL Intel® FPGA IP Upgrade in the Intel® Stratix® 10 E-Tile Triple-Speed Ethernet Intel® FPGA IP Design Example? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, you may see the IOPLL Intel® FPGA IP is not upgraded successfully in the Triple-Speed Ethernet Intel® FPGA IP 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE1588v2 and 2XTBI PCS with E-Tile GXB Transceiver Design Example. Without performing the IOPLL Intel® FPGA IP Upgrade, the following errors will be seen when compiling the example design: Error(18185): Your design contains IP components that must be regenerated. To regenerate your IP, use the Upgrade IP Components dialog box, available on the Project menu in the Quartus Prime software Error(18186): You must upgrade the IP component instantiated in file ip/alt_tse_iopll_todsampling_clk.ip to the latest version of the IP component. Error(18186): You must upgrade the IP component instantiated in file ip/alt_core_iopll_upstream.ip to the latest version of the IP component. Error(18186): You must upgrade the IP component instantiated in file ip/alt_core_iopll_tse_rx_clk.ip to the latest version of the IP component. Error(18186): You must upgrade the IP component instantiated in file ip/alt_core_iopll_tse_clk.ip to the latest version of the IP component. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition Software version 21.2, follow the steps below. Perform the IP upgrade and regenerate the IOPLL Intel® FPGA IP components. Open the simulation script for the simulator of your choice: Modelsim* -/example_testbench/setup_scripts/common/modelsim_files.tcl VCS* - /example_testbench/setup_scripts/common/vcs_files.tcl VCSmx* - /example_testbench/setup_scripts/common/vcsmx_files.tcl Xcelium* - /example_testbench/setup_scripts/common/xcelium_files.tcl Edit the four IOPLL Intel® FPGA IP design file names in the simulation script to match with the regenerated IOPLL Intel® FPGA IP component design file names. Examples of the IOPLL Intel® FPGA IP design files names with random string suffix that need to be updated. alt_core_iopll_tse_clk_altera_iopll_1931_oppet4q.vo1 alt_core_iopll_tse_rx_clk_altera_iopll_1931_t57sz6i.vo1 alt_core_iopll_upstream_altera_iopll_1931_4pedkla.vo1 alt_tse_iopll_todsampling_clk_altera_iopll_1931_7vfkdfa.vo1 Save the files. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.3. Custom Fields values: ['novalue'] Troubleshooting 1509353420 True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.3 21.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']