Why does the Frame Buffer MegaCore not generate simulation model from Qsys? - Why does the Frame Buffer MegaCore not generate simulation model from Qsys?
Description In Quartus® II software version 12.1, when trying to “Create Simulation Model” in Qsys for the Frame Buffer MegaCore®, you may receive the following error messages: Error: Unable to generate simulation model for testFB_alt_vip_vfb_0 Error: Generation stopped, 1 or more modules remaining Error: ip-generate failed with exit code 1: 8 errors, 0 warning These error messages indicate that Qsys is unable to generate the simulation model for the Frame Buffer MegaCore and causes the Qsys system generation to fail. Resolution This issue is fixed in Quartus II software version 13.0.
Custom Fields values:
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Troubleshooting
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False
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['FPGA Dev Tools Quartus II Software']
13.0
12.1
['Programmable Logic Devices']
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['novalue']
['novalue'] - 2021-08-25
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