Why do I see clock crossing timing failures for the rx_lanes_aligned signal in the Interlaken (2nd Generation) Intel® FPGA IP design example? - Why do I see clock crossing timing failures for the rx_lanes_aligned signal in the Interlaken (2nd Generation) Intel® FPGA IP design example? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 21.1 and earlier, the rx_lanes_aligned signal was not synced to usr_clk before exiting to the intellectual property (IP) core. This can cause metastability at the user logic if it is not synchronized by the user. The metastable issue can propagate to the user logic even if the change of aligned is not frequent. Resolution To work around this, Intel recommends adding a s ynchronizer to the rx_lanes_aligned signal onto the usr_clk domain. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 22.3. Custom Fields values: ['novalue'] Troubleshooting 1508954532 1508954811 True ['Interlaken (2nd Generation) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 21.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 DX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 NX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']