Why is the power estimation of HPS core power rails inaccurate? - Why is the power estimation of HPS core power rails inaccurate? Description Due to a problem in the Power & Thermal Analyzer and Quartus Power Analyzer version 25.3.1 and earlier, the power estimation of HPS core power rails (VCCL_HPS, VCCL_HPS_CORE0_CORE1, VCCL_HPS_CORE2 and VCCL_HPS_CORE3) for Agilex® 3, Agilex® 5 and Agilex® 7 FPGA devices might be inaccurate if the CPU frequency field in PTA is empty or contains the wrong frequency. Resolution To work around this problem, manually import existing PTC/PTA/QPTC/QPTA files into the Power & Thermal Analyzer and ensure the CPU frequency field is filled with the correct frequency value: For Agilex 7 FPGA devices, ensure the CPU frequency field contains the highest CPU frequency used in your design For Agilex 3 and Agilex 5 FPGA devices, ensure the CPU frequency field contains the DSU frequency of your design. The DSU frequency is the highest CPU frequency (A55/A76 core frequency) used in your design divided by 1.5 This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 14027177917 novalue ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex™ 3 FPGAs and SoCs', 'Agilex™ 5 FPGAs and SoCs', 'Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']