Why do I see dropped Read or Write requests when simulating the Hard IP for PCI Express Avalon®-MM DMA core? - Why do I see dropped Read or Write requests when simulating the Hard IP for PCI Express Avalon®-MM DMA core? Description Due to a problem with the testbench generated by the IP Catalog or Platform Designer, you will see dropped transactions if your test issues closely spaced (back to back) memory reads or writes from the Endpoint (to the Rootport). This applies to the Avalon® memory mapped with DMA variants. Resolution To work around this problem, increase the time between your upstream requests. Intel recommends using a third-party commercial Root Port Bus Functional Model (BFM) for production verification of the PCIe Hard IP. This problem is not scheduled to be fixed in a future Intel® Quartus® Prime Software release. Custom Fields values: ['novalue'] Troubleshooting - False ['DMA', 'Simulation'] ['FPGA Dev Tools Quartus II Software'] novalue No plan to fix ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']