Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies? - Why do F-tile Reference and System PLL clocks Intel® FPGA IP fail to lock at specific frequencies? Description Due to a problem in In the Intel® Quartus® Prime Pro Edition Software versions 22.2 and earlier, you might observe the F-tile Reference and System PLL clocks Intel® FPGA IP fails to lock at: 999.9 MHz with the reference clock frequency set as 323.2 MHz. 506.88 MHz with the reference clock frequency set as 245.76 MHz. Resolution To work around this problem, you need to do the following steps: In the project navigator, double-click the OPN (ordering part number). In the pop-out window, click the “Device and Pin Options” button. In the “General” category, change the “Configuration clock source” parameter from “Internal Oscillator” to: 100 MHz OSC_CLK_1 pin, or 125 MHz OSC_CLK_1 pin Recompile the design . Provide an external reference clock with the correct frequency to the OSC_CLK_1 pin. The “OSC_CLK_1” pin location can be found in the schematics of your development kit. Note: for Intel Agilex® F-tile devices with OPNs that end with the suffix VR0, VR1, and VR2, you need to use Intel® Quartus® Prime Programmer version 21.4 to get the above workarounds working. Custom Fields values: ['novalue'] Errata 15010796894 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.3 22.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']