100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design - TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel® Stratix® 10 GX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Cyclone® 10 GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Aerospace ASIC Proto Defense Medical Transportation 100G TCP/IP Stack for Network Acceleration - MLE FPGA IP Core Design Key Features Highly modular TCP/UDP/IP stack implementation in synthesizable HDL a1JUi0000049UJMMA2 Offering Brief No No No Yes Encrypted Verilog Encrypted VHDL Verilog VHDL Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel® Stratix® 10 GX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel® Stratix® 10 SX SoC FPGA Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel® Cyclone® 10 GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Stratix® III FPGA Yes No 25.1.1 Offering Brief Production a1JUi0000049UJMMA2 What's Included a1JUi0000049UJMMA2 Modular and application-specific 100G TCP/IP cores Ordering Information napa-100G a1JUi0000049UJMMA2 Production Design Services Intellectual Property (IP) a1MUi00000BO8sfMAD a1MUi00000BO8sfMAD Select 2025-11-24T16:48:38.000+0000 TCP/IP full accelerator for 100G TCP/IP connections. Including TCP, IP, MAC Layer. 128-bit wide full duplex data width pipelined all-RTL implementation for ultra-low latency. Partner Solutions