Can I use a transceiver RX Pin as a CDR REFCLK for the HDMI Design Example Receiver Interface (Sink) on Arria® 10 and Cyclone® 10 devices? - Can I use a transceiver RX Pin as a CDR REFCLK for the HDMI Design Example Receiver Interface (Sink) on Arria® 10 and Cyclone® 10 devices? Description No, you cannot use a transceiver RX Pin as a CDR REFCLK for the HDMI™ Design Example Receiver Interface (Sink) on Arria® 10 and Cyclone® 10 devices. The HDMI TMDS_CLK frequency is dependent on the video resolution. Low resolutions have a TMDS_CLK frequency of 27MHz below the minimum CDR REFCLK frequency. The HDMI Design Example implements a cascaded IOPLL architecture to multiply up the TMDS_CLK for low-resolution video. TMDS_CLK -> IOPLL -> CDR REFCLK The RX Pin as a REFCLK feature can only be used when connected directly to the CDR REFCLK. Your design will fail to fit in the Intel® Quartus® Prime Software if you place the HDMI Design Example RX REFCLK on an Rx Pin. Resolution To work around this problem you should place your HDMI Design Example TMDS_CLK on a dedicated transceiver REFCLK pin. Custom Fields values: ['novalue'] Troubleshooting FB: 489720; False ['HDMI'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.0 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']