Incorrect Connections Shown in SOPC Builder Illustration in PCI Express Compiler User Guide - Incorrect Connections Shown in SOPC Builder Illustration in PCI Express Compiler User Guide Description Figure 16-3, Port Connections in the PCI Express Compiler User Guide is missing a connection from the dma_0 read_master to the onchip_memory2_0 s1 . In addition, it shows an incorrect connection from the pcie_compiler_0 bar2_Non_Prefetchable to onchip_memory2_0 s1 . This is a documentation error only. The following figure illustrates the correct connections. System Port Connections Resolution No workaround is required. Make the connections described in Table 16-6, SOPC Builder Connections, in the IP Compiler for PCI Express User Guide This issue is fixed in version 11.0 of the IP Compiler for PCI Express User Guide . Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.0 10.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']