Timing Analysis for PCI Express Compiler × Variations That Target a Cyclone IV GX Device - Timing Analysis for PCI Express Compiler × Variations That Target a Cyclone IV GX Device Description The Quartus II software does not perform timing analysis for the FPGA fabric in Cyclone IV GX × variants; consequently, variants that would fail timing analysis are not identified. This issue affects × variants in the Cyclone IV GX device. Resolution You can manually create the required clock constraint. provides the equation for this constraint. In this equation <n> is 8.000 for a 125 MHz application clock and 16 for a 62.5 MHz application clock. Clock Constraint # create_clock -name {core_clk_out} -period <n> -waveform { 0.000 8.000 } [get_nets {*altpcie_hip_pipen1b_inst | core_clk_out~clkctrl}] This issue is fixed in version 10.1 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.1 10.0 ['Cyclone® IV FPGAs'] ['novalue'] ['novalue'] ['novalue']