When using Windows* why does the Intel® Stratix® 10 Avalon® Memory Mapped Hard IP for PCIe* Design Example fail to generate? - When using Windows* why does the Intel® Stratix® 10 Avalon® Memory Mapped Hard IP for PCIe* Design Example fail to generate? Description Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.2 and earlier for Windows*, the Intel® Stratix® 10 Avalon® Memory Mapped Hard IP for PCIe* Design Example fails to generate correctly. Resolution There is no workaround for this problem. The design example can be generated correctly with the Linux* version of the Intel® Quartus® Prime Pro Edition software version 19.2. This problem has been fixed for Windows* starting with the Intel® Quartus® Prime Pro Edition software version 19.3 and later. Custom Fields values: ['novalue'] Troubleshooting 14010602731 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.3 19.2 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']