When performing Link Disable-Enable loop testing with the R-Tile Avalon® Streaming FPGA IP for PCI Express*, why does the host system report Polling.Active timeout failures? - When performing Link Disable-Enable loop testing with the R-Tile Avalon® Streaming FPGA IP for PCI Express*, why does the host system report Polling.Active timeout failures? Description Due to a problem in the R-Tile Avalon® Streaming FPGA IP for PCI Express*, Host systems may report Polling.Active timeout failures when running LTSSM Link disable-enable loop tests. This failure is limited to Port 0 of the R-Tile Avalon® Streaming FPGA IP for PCI Express*. Resolution This problem has no functional implication, and is not planned to be fixed in a future version of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15014701914 False ['R-Tile Avalon-ST for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 23.2 ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']