Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction? - Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction? Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n ). This is because the synthesis attributes " LVDS_RX_REGISTER=LOW " and " LVDS_RX_REGISTER=HIGH " are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File ( .qsf ): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15013902081 False ['ALTLVDS_RX'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 23.1 ['Arria® II FPGAs', 'Arria® V GZ FPGA', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 LP FPGA', 'MAX® 10 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']