Why does Modelsim*/Questasim* simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM DMA Interface for PCI Express* fail with X propagation problem in the Read Data Mover (altpcieav_dma_rd.sv) module? - Why does Modelsim*/Questasim* simulation of the Intel® Arria® 10 or Intel® Cyclone® 10 GX Avalon®-MM DMA Interface for PCI Express* fail with X propagation problem in the Read Data Mover (altpcieav_dma_rd.sv) module? Description The root cause of this X propagation problem is that the LPM_DEST_ADD_SUB_component instantiation in the Read Data Mover ( altpcieav_dma_rd.sv ) module does not have its .datab port properly zero-extended to the full signal vector width. Therefore, the simulator assigns X's to the leading unassigned bits in the destination address. Refer to the LPM_DEST_ADD_SUB_component instantiation below. ********************************************************************************************************************************* lpm_add_sub LPM_DEST_ADD_SUB_component ( .clken (1'b1), .clock (Clk_i), .dataa (cur_dest_addr_reg), .datab ({rd_dw_size, 2'b00}), .result (cur_dest_addr_adder_out) // synopsys translate_off , .aclr (), .add_sub (), .cin (), .cout (), .overflow () // synopsys translate_on ); defparam LPM_DEST_ADD_SUB_component.lpm_direction = "ADD", LPM_DEST_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO", LPM_DEST_ADD_SUB_component.lpm_pipeline = 1, LPM_DEST_ADD_SUB_component.lpm_representation = "UNSIGNED", LPM_DEST_ADD_SUB_component.lpm_type = "LPM_ADD_SUB", LPM_DEST_ADD_SUB_component.lpm_width = RDDMA_AVL_ADDR_WIDTH; ********************************************************************************************************************************* Resolution The workaround is to properly zero-extend the .datab port's input signal vector as shown below. .datab ({ {(RDDMA_AVL_ADDR_WIDTH-12){1'b0}}, rd_dw_size, 2'b00}), This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime software. Custom Fields values: ['novalue'] Troubleshooting FB: 562904; False ['Arria® 10 Cyclone® 10 Hard IP for PCI Express', 'PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0.1 17.1.2 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 GX FPGA'] ['novalue'] ['novalue'] ['novalue']