EMIF HPS errors after upgrading to Quartus 25.3 - EMIF HPS errors after upgrading to Quartus 25.3 So I'm trying to upgrade an Agilex-5 project from Quartus 25.1 to 25.3 but the project no longer compiles with errors relative to the EMIF HPS IP. I'm using an Agilex 5 FPGA E-Series 065B Premium Devkit. The project was based in the GSRD for Quartus 25.1 (QPDS25.1_REL_GSRD_PR) and had a few modifications, working in version 25.1. Firstly, when upgrading to Quartus 25.3, the auto-update does not work with errors to the Agilex-5 HPS IP and EMIF HPS IP. I'm forced to upgrade manually which also results in errors but fixed with this workaround: https://www.intel.com/content/www/us/en/support/programmable/articles/000102053.html In the end I can Generate HDL sources from Platform Designer but compilation stops with errors in the Fitter stage: I've noticed that the new EMIF HPS IP version has a difference in the signal mem_0_bg that only has 1 bit in the latest version but was 2-bit wide in the previous versions. I don't know if the problem comes from this: Another interesting thing that I found is that in the latest GSRD project (QPDS25.3_REL_GSRD_PR) the EMIF HPS IP used is not the latest version (4.1.0) but a previous one (4.0.0). So I'm guessing someone from Altera already discovered some sort of problem here: Looking for advice on how to proceed. Replies: Re: EMIF HPS errors after upgrading to Quartus 25.3 Hello AdzimZM_Altera , Thanks for the pointers, it was indeed the pin swizzling and other parameters hidden inside the "Dive into Packaged Subsystem" of the EMIF HPS IP. Initially after I upgraded the EMIF HPS IP, it appeared without any interfaces: So I deleted the component and instantiated a new one but apparently caused all the hidden parameters to be reset. I was assuming these hidden parameters would be automatically set since Quartus knows I'm using a devkit. Replies: Re: EMIF HPS errors after upgrading to Quartus 25.3 Hello pmarques , Do you have any feedback in this thread? Regards, Adzim Replies: Re: EMIF HPS errors after upgrading to Quartus 25.3 Hello, Can you check in the design for pin placement of the user reference clock? Is it placed in Bank 3A? Can you check for the pin swizzling parameter in the EMIF HPS IP? Regards, Adzim