Why does the Intel® Low Latency 40-GbE IP core fail Auto-Negotiation when the master lane is selected as 0, 1, or 3? - Why does the Intel® Low Latency 40-GbE IP core fail Auto-Negotiation when the master lane is selected as 0, 1, or 3? Description Due to a problem in the Intel® Arria® 10 Low Latency 40GBASE-KR4 logic implementation, Auto-Negotiation(AN) may fail prior to Intel Quartus® Prime softwar version 16.0 update1. The IP core might fail AN if the master lane is selected as 0, 1, or 3, due to timing issues internal to the core. As this problem is caused by a timing issue, simulation will work correctly. Resolution To work around this problem, set the master lane as 2. This problem has been fixed in the Intel Quartus Prime software version 16.0 update 1. Custom Fields values: ['novalue'] Troubleshooting FB: 320048, 363302, 367061, 372500; True ['Low Latency 40G 100G Ethernet', 'Low Latency 40G Ethernet IP for Arria® 10 and Stratix® V'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 16.0.1 15.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']