Why can I assign more than a 32-bit data width to the Arria® V Hard Memory Controller? - Why can I assign more than a 32-bit data width to the Arria® V Hard Memory Controller? Description Although the Arria® V handbook states that the A1, A3, A5, and A7 devices can support up to a 32-bit width controller on top or bottom edges, the Quartus® II software incorrectly allows you to implement a 40-bit controller without an error message. Resolution Please follow the document to set the data width up to 32 bits. Custom Fields values: ['novalue'] Troubleshooting 2205836119 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']