Why won’t the “refclock_status”, “out_systempll_synthlock_i” and “refclk_fgt_enabled_i” ports assert on the F-Tile Reference and System PLL Clocks IP variant? - Why won’t the “refclock_status”, “out_systempll_synthlock_i” and “refclk_fgt_enabled_i” ports assert on the F-Tile Reference and System PLL Clocks IP variant? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the “refclock_status”, “out_systempll_synthlock_i” and “refclk_fgt_enabled_i” ports may fail assert on the F-Tile Reference and System PLL Clocks IP variant when the “Refclk #i is active at and after device configuration” parameter is not enabled. Resolution There is no workaround for this problem. This problem have been fixed in the Quartus® Prime Pro Edition Software version 24.3. Custom Fields values: ['novalue'] Errata 18039694602 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']