keeping signals for signaltap - keeping signals for signaltap Hi, I'm using Quartus prime lite edition (language VHDL). how can I "keep" signals so they appear in the siganltap search? Replies: Re: keeping signals for signaltap Hi, May be can try with attribute noprune check this https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vhdl/vhdl_file_dir_noprune.htm , adding virtual pins in the Assignment Editor or use "pre-synthesis" filter in SignalTap's node selector and tapped the signal inside a "component" rather than in the top-entity where it is generated. Thanks, Best regards, Sheng p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey. Replies: Re: keeping signals for signaltap some internal signals in my project (flag, counter, etc) Replies: Re: keeping signals for signaltap What exactly are you trying to tap? Replies: Re: keeping signals for signaltap I tried the "keep" and/or "preserve" (I always look for pre-synthesis) and doesn't work.. Replies: Re: keeping signals for signaltap If you want to preserve signals to tap as post-fit signals, you can use the "keep" and/or "preserve" synthesis attributes in your HDL code. There is a preserve for debug feature that uses project assignments, but that's only in the Pro edition of the tool. You can also just tap the signals pre-synthesis, basically tapping the signals directly from your RTL code.