Stratix V Avalon-MM Hard IP for PCI Express IP Core Testbench Generation Fails - Stratix V Avalon-MM Hard IP for PCI Express IP Core Testbench Generation Fails Description Testbench generation fails for the Avalon-MM Hard IP for PCI Express IP core in the 11.1 SP2 release. The failure is caused by a signal mismatch on the PIPE interface. The bus functional model (BFM) includes two new signals on the PIPE interface: txmargin and txswing which the Avalon-MM Hard IP for PCI Express IP core does not include. Resolution The workaround is to add the txmargin and txswing signals to the Avalon-MM Hard IP for PCI Express IP core by generating the testbench and the msim_setup.tcl script from the command line. Type the following commands in the directory that includes your .qsys file, referred to as <my_system>.qsys: sopc_builder --script="/sopc_builder/bin/tbgen.tcl" <my_system>.qsys ip-generate --file-set=SIM_VERILOG --system-info=DEVICE_FAMILY="Stratix V" --report-file=spd:top_tb.spd --component-file=<my_system>_tb.qsys ip-make-simscript --spd=top_tb.spd The msim_setup.tcl script is created in the mentor directory. This issue is fixed in release 12.0 of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 12.0 11.1.2 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']