Multi-Rate Ethernet PHY FPGA IP - The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device… Altera, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of… Arria® V GT FPGA Arria® V GX FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® III FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 TX FPGA The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. This IP allows dynamic reconfiguration across all Ethernet rates from 10M, 100M, 1G, 2.5G, 5G, and 10G. It handles the frame encapsulation and flow of data between a client logic and Ethernet network via PCS and PMA (PHY). Ethernet Access Aerospace ASIC Proto Broadcast Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Government Industrial Medical Test Transportation Wireless Multi-Rate Ethernet PHY FPGA IP Key Features Implements the Ethernet protocol as defined in clause 36 of the IEEE 802.3 2005 standard Offering Brief No No No Yes Encrypted Verilog Arria® V GT FPGA Arria® V GX FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® III FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 TX FPGA Yes Yes Offering Brief Production a1JUi0000049UUtMAM What's Included Encrypted Verilog source code Ordering Information IP-10GMRPHY Digikey Mouser a1JUi0000049UUtMAM Production Intellectual Property (IP) a1MUi00000BO8twMAD a1MUi00000BO8twMAD 2026-04-21T12:58:34.000+0000 The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates from 10M to 10GbE in accordance with the IEEE 802.3 Ethernet Standard without any design regeneration or device reconfiguration. Altera Solutions