Serdes Ref clk input circuit - Serdes Ref clk input circuit I would like to see the equivalent input circuit for the Serdes clock diff inputs. Is it HSTL maybe? I only found reference to what is compatible with the input like PECL, LVDS etc. This is for 5CGXFC7D6F27 part. Thanks Replies: Re: Serdes Ref clk input circuit Ok I got it Thanks! I marked it done. Replies: Re: Serdes Ref clk input circuit Hi, Yes, Cyclone V receiver buffer does has internal on-chip biasing circuitry but we can't expose the internal circuit design as it's Intel proprietary design info. However, we do have user guide doc that explained on available feature in receiver buffer. You can checkout chapter "Recevier PMA datapath" (Page 20) in below user guide link https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_53004.pdf Thanks. Regards, dlim Replies: Re: Serdes Ref clk input circuit Deshi, I don't understand how your IC can take either ground referenced signals or biased signals. Do you have a blocking cap inside? I was hoping for an equivalent circuit schematic if you have one. Thanks Replies: Re: Serdes Ref clk input circuit HI, You can refer to Cyclone V datasheet (table 21, page 25) for the supported IO standard for transceiver refclk pin. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf#page=25&zoom=100,0,0 I can see some of the IO standard that you mentioned but I don't see HSTL is a supported IO standard in the list. Pls switch to use supported IO standard as mentioned in Cyclone V datasheet. Thanks. Regards, dlim